1. Technical Field
The present invention relates generally to the field of integrated circuits. In particular, this invention relates to power supplies for integrated circuits and to an improved and simplified method for providing a stable source of power for a complementary metal oxide semiconductor (CMOS) integrated circuit utilizing a split-rail or dual power supply.
2. Related Art
The field of integrated circuitry is a rapidly developing field of technology. Integrated circuits are continually being made smaller with the attendant requirements of increasing both device speed and circuit density. The miniaturized devices built within and upon a semiconductor substrate are spaced very closely together and the integrated circuit density, that is, the number of integrated circuits per unit of surface area, continues to increase significantly. The highest integrated circuit density is achieved using Field Effect Transistors (FETs). A FET is a device having a source, gate, and drain arranged such that when a high logic signal voltage is applied to the gate, current may pass from the source to the drain. Similarly, a FET does not allow current to pass between the source and the drain when a low logic signal is applied to the gate.
As the integrated circuit density increases, the amount of power dissipated by the integrated circuits on the substrate increases proportionally. The amount of power dissipation is a concern because complicated heat sinks and circuit packaging may be required to prevent the chip temperature from rising above its rated operational temperature limit. Further, many devices containing integrated circuits typically operate on stored power. One example is a portable computer operating on battery power. As power dissipation increases, battery life decreases, and the shorter the operational life of the electronic device. Therefore, reducing the power consumption for a given integrated circuit density is important to the design of integrated circuits.
One way to decrease this power consumption is to reduce the voltage at which the circuits operate. However, decreasing the operational voltage level creates a compatibility problem because some integrated circuits are designed to operate at predetermined, specific voltage levels. For example, some circuits may interface with low voltage circuits, and these same circuits may need to operate at higher voltage levels to operate electro-mechanical devices. Also, there are many existing integrated circuits that cannot have their operating voltage altered, and yet, new, lower voltage circuits must interact with them. Therefore, in order to lower the voltage of integrated circuits so that they dissipate less power, and still permit their interaction with different or existing hardware, some form of interface circuitry is required.
The related art has provided a variety of interface circuits for translating lower voltage levels into higher voltage logic levels and vice versa. This is primarily due to the fact that logic voltage levels implemented in integrated circuits have been steadily decreasing as technologies evolve.
In general, complementary metal oxide semiconductor (CMOS) integrated circuits require more than one power supply per chip. Such designs are known in the art as xe2x80x9csplit rail designs.xe2x80x9d For instance, a split rail design is utilized when the internal or core chip voltage, VDD, operates at a different voltage level than the input/output (I/O) interface voltage, or the output driver voltage, OVDD. The integrated circuit core voltage, VDD, is limited by the integrated circuit technology or power dissipation requirements of the chip, as well as the driver output voltage, OVDD.
Split rail designs create many challenges that must be addressed by both integrated circuit designers and system designers. For a typical split rail integrated circuit to operate properly, both of the power supplies must be in their powered-up state. Numerous problems can occur when one supply is xe2x80x9coffxe2x80x9d while the other is xe2x80x9con.xe2x80x9d Problems can also occur when the sequence in which the two supplies are powered up or powered down becomes critical.
One example of such a problem occurs when the integrated circuit core voltage, VDD, is in an off state and the output drivers are powered up via the output driver voltage, OVDD. In this situation, the output drivers will have lost all the control signals from the integrated circuit core which are derived from the integrated circuit core voltage, VDD. With no control signals to the drivers, the drivers"" output stages may try to pull the output pad both up and down at the same time. This scenario is characterized by a high crossover current effect from the output driver voltage, OVDD, to ground, which can be multiplied by hundreds of drivers throughout the chip thereby causing permanent equipment damage.
This problem has been solved in the related art by requiring power supply sequence rules that dictate that the internal chip voltage VDD must power up before the driver voltage OVDD. This ensures that there are valid logic levels at the xe2x80x9cDATAxe2x80x9d and xe2x80x9cENABLExe2x80x9d inputs of the driver before the driver is powered up. A power-down sequence is also required such that the OVDD is powered down before VDD for the same reasons described in the power-up sequence.
There is also the case wherein there is a sudden loss of VDD after both supplies are up and running. This can be due to the VDD supply failing and causing the high current condition in the output drivers. For this final case, there must be some intelligence in the system that forces OVDD off if there is a sudden and permanent loss of VDD.
This level of sophistication is not always available in power supplies used to power integrated circuits. The solution this invention provides places no restrictions on power supply sequence or the sudden loss or failure of a power supply. This small amount of circuitry added to the driver design is noninvasive, and therefore will not affect driver performance.
The present invention solves these problems in the related art by breaking the series path through the driver""s output stage when the core voltage is detected to be xe2x80x9coff.xe2x80x9d The conduction path between OVDD and GND is broken, thereby eliminating the potential for damage and eliminating the need for power supply sequencing requirements. The invention also protects against the sudden loss of the VDD power supply during otherwise normal operation.
The present invention provides a semiconductor chip, comprising: a first plurality of circuits connected to a first voltage contact having a first voltage potential, and to a ground contact; a second plurality of circuits connected to a second voltage contact having a second voltage potential, and to said ground contact; a detection circuit connected to said first voltage contact, said second voltage contact, and said ground contact, and having an output node; said detection circuit adapted to operate by detecting the loss of voltage potential at said first voltage contact; said detection circuit adapted to pull said output node to said second voltage potential when said first voltage potential and said second voltage potential are both present; and said detection circuit adapted to pull said output node to ground potential when said first voltage potential is not present.
Another aspect of the invention is to provide a semiconductor interface circuit for translating lower voltage logic levels into higher voltage logic levels, comprising: a first voltage contact; a second voltage contact; a ground contact; a sensing circuit which monitors the voltage levels at the first and second voltage contacts; and a detection circuit having an output node, and adapted to force said output node to ground potential, only when a second voltage source is connected to said second voltage contact and no voltage source is connected to said first voltage contact; and wherein the semiconductor interface circuit is adapted to enter a high impedance state when said output node is pulled to said ground potential at the ground contact.
The present invention also presents a method of protecting circuitry in a semiconductor chip, comprising: providing a first plurality of circuits connected to a first voltage contact and a ground potential contact; providing a second plurality of circuits connected to a second voltage contact and said ground potential contact; providing a detection circuit connected to said first voltage contact and said second voltage contact, and having an output node, said detection circuit operating by forcing said output node to said ground potential contact only when a second voltage source is connected to said second voltage contact and no voltage source is detected at said first voltage contact; and connecting at least one of said second plurality of circuits to said output node of said detection circuit.
The present invention further provides a two-supply input/output protection circuit comprising: a driver input stage having a data input and an enable input; a detection stage having a pre-drive stage comprising a NAND gate and a NOR gate, said detection stage operationally connected to an output of said input stage; an output stage operationally connected to an output of the pre-drive stage; and a loss detection stage having an inverter stage and a voltage bias stage, said inverter stage operationally connected to said driver input stage, and said voltage bias stage operationally connected to said output stage.
The present invention additionally provides a two-supply input/output protection circuit comprising: a driver input stage having a data input and an enable input; a detection stage having a pre-drive stage comprising a NAND gate and a NOR gate, said detection stage operationally connected to an output of said input stage; an output stage operationally connected to an output of the pre-drive stage; a loss detection stage having an inverter stage and a voltage bias stage, said inverter stage operationally connected to said driver input stage, and said voltage bias stage operationally connected to said output stage; and an inverting levels translation circuit for detecting the loss of a first voltage potential.
The foregoing and other features of the invention will be apparent in the following and more particular description of the embodiments of the invention as illustrated in the accompanying drawings.